The Orange Pi RV2 is a RISC-V development board - HTTAY 125 Sylph

#httay #orangepi #opensource #openhardware #risc-v #development #technology

https://youtu.be/jt77v-N3ldA?si=CYasJd6ItBYyhiPn

If I had the income, I'd get a #pocketreform in a heartbeat and slap it with it's case into my Steam Deck sling back, enjoying it on top of a mountain during a hike.
#risc #mntre

Have a couple more openings on my team for folks if you want to come play:

First up is a Rust developer, mostly working on things like Luwen and working on moving some of our python based tools down to rust based tools. Lots of things coming, and all down in the systems stack.

https://job-boards.greenhouse.io/tenstorrent/jobs/4736078007

Second up is someone to come work on the OSPO side of things, day to day chasing stuff down on that front, getting out ahead, policy stuff, and some side scripting to help make things in a few directions better.

https://job-boards.greenhouse.io/tenstorrent/jobs/4736080007

Solid team, lots of interesting problems, and we are working in the open on open source tooling for things here.

Worth taking a look!

#FediHire #Tenstorrent #RISC-V #RISCV #AI

silly question:

how many instructions and registers would a minimal RISC be?

load, store, move, add, sub, nop, jump, beq, blt, and, or, xor, not, shift left, shift right, mul, div, rem, min, max, call, ret, sys, int?

general purpose, return addr, stack pointer, func args(x?), saved registers(x?),

maaaybe a time register and identity register, an interrupt masks register that can only be written by a privileged process... so a ring register?

I wonder how DEC Alpha compares to RISC-V, given the age gap. #risc

Over 250 billion Arm chips have shipped since the first #ARM1 processor launched 40 years ago
ARM1 #CPU ended up being a pioneering #RISC chip, featuring just 6,000 gates, while modern Arm processors feature more than 100 million.
Arm admits that the signature quality of its chips – their energy efficiency – was driven out of frugality they couldn't afford ceramic chip packaging so had to be very strict about efficiency, so plastic packaging would be acceptable.
https://www.tomshardware.com/pc-components/cpus/over-250-billion-arm-chips-have-shipped-since-the-first-arm1-processor-launched-40-years-ago

Angelina Jolie Was Right About Computers | WIRED

｢ China’s top scientists have heralded RISC-V as a path to silicon independence. India just used RISC-V to make its first homemade microprocessor. Name a country; it’s probably experimenting with RISC-V. Brazil sent a record 25 delegates to the RISC-V summit ｣

https://www.wired.com/story/angelina-jolie-was-right-about-risc-architecture/

Loving the days when I get the IPX Up and running (scheduled function test any 6 months)

RISC-V RVA23 Profile: A major milestone

https://riscv.org/ecosystem-news/2025/04/risc-v-rva23-a-major-milestone/

#HackerNews #RISC-V #RVA23 #RISCVMilestone #TechNews #OpenSource

A 32-bit processor made with an atomically thin semiconductor

https://arstechnica.com/science/2025/04/researchers-build-a-risc-v-processor-using-a-2d-semiconductor/

#HackerNews #32bitProcessor #AtomicallyThin #Semiconductor #RISC-V #Technology #Innovation

Run RISC-V Binaries on AMD Zen-Series CPUs via Microcode Modification

https://rvspoc.org/en/S2502/

#HackerNews #RISC-V #AMD #Microcode #Zen-Series #Binaries #Technology

Ubuntu unterstützt günstigen RISC-V SBC
https://linuxnews.de/ubuntu-unterstuetzt-guenstigen-risc-v-sbc/ #risc-v #ubuntu #orangepi #sbc #linux

RISC architecture is gonna change everything

https://video.infiniteloop.tv/videos/watch/7e52e6b9-b24b-4505-a34e-d066e8f3f9f8

#Europe bets on #RISC-V for homegrown supercomputing platform
https://www.theregister.com/2025/03/07/dare_europe_risc_v_project/

"Do you #DARE? Europe bets once again on RISC-V for #supercomputing #sovereignty
€240M found for three-year sprint to develop three chiplets for #HPC, #AI"

If the #EU would take this serious, that should have been Billions instead if Millions. And not a 3y sprint.

This would be really worth the investment. We need much more than that. Yesterday.

Back in all it's glory ...

Reviving a SPARCstation IPX ... recapped PSU is working

#Fedora ist bereit für #RISC_V

RISC-V ist eine offene Befehlssatzarchitektur (Instruction Set Architecture, #ISA), die auf den Prinzipien von Reduced Instruction Set Computing ( #RISC ) basiert. Im Gegensatz zu proprietären Architekturen ist RISC-V kostenlos und offen. Im Hinblick auf Offenheit und Freiheit ist die Entwicklung von RISC-V-Hardware für #Linux ein wichtiger Schritt.
Zielsetzung primäre Architektur.

https://linuxnews.de/fedora-ist-bereit-fuer-risc-v/