Topaz 🐇<p>OK this is pretty cool. A project called DigitalJS can give you a visual layout of all of the logic that'll go into a Verilog design, using Yosys to do the generation. Being able to see what's being ultimately produced helps me, a much more visual person, understand when I've flubbed something that generates too much logic. I already optimized one piece of the display RAM using it. It's at <a href="https://digitaljs.tilk.eu/" rel="nofollow noopener" translate="no" target="_blank"><span class="invisible">https://</span><span class="">digitaljs.tilk.eu/</span><span class="invisible"></span></a> but you can also run it locally. <a href="https://oldbytes.space/tags/fpga" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>fpga</span></a> <a href="https://oldbytes.space/tags/verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>verilog</span></a> <a href="https://oldbytes.space/tags/ulx3s" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>ulx3s</span></a></p>
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#verilog
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poleguy looking for lost tools<p>The search engines are failing me.</p><p>Dear Lazy Web:<br>If I wanted to enumerate the hierarchy of a design at the beginning of a cocotb test bench, how would I do it? (I'm aware of _discover_all(), but can't figure out how to iterate the results to print them.)</p><p>Extra credit: How do I get an interactive debugger to break within the cocotb python code if I call cocotb from pytest? It seems to run the pytest code in the debugger, but not the cocotb code.</p><p><a href="https://mastodon.social/tags/fpga" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>fpga</span></a> <a href="https://mastodon.social/tags/cocotb" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>cocotb</span></a> <a href="https://mastodon.social/tags/lazyweb" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>lazyweb</span></a> <a href="https://mastodon.social/tags/python" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>python</span></a> <a href="https://mastodon.social/tags/vhdl" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>vhdl</span></a> <a href="https://mastodon.social/tags/verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>verilog</span></a></p>
bleeptrack<p>If you wanna see me struggle with <a href="https://vis.social/tags/shaders" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>shaders</span></a> and <a href="https://vis.social/tags/verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>verilog</span></a> at the same time: I have a stream for you this evening!</p><p><a href="https://www.youtube.com/live/HSV3xF_TSqg?si=YmyPzEyXG5p8ryU1" rel="nofollow noopener" translate="no" target="_blank"><span class="invisible">https://www.</span><span class="ellipsis">youtube.com/live/HSV3xF_TSqg?s</span><span class="invisible">i=YmyPzEyXG5p8ryU1</span></a></p>
Holly A. Gultiano<p>All the equivalent circuit models of neurons written in an <a href="https://synapse.cafe/tags/verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>verilog</span></a> would be a cool project</p>
Jack<p>Hey all! I'm due for an (re-)introduction: I'm Jack, an engineer in the NYC area from a firmware & cybersecurity background, currently working in something like hardware-software co-design.</p><p>Technical work is often with <a href="https://recurse.social/tags/rust" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>rust</span></a> <a href="https://recurse.social/tags/kicad" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>kicad</span></a> <a href="https://recurse.social/tags/python" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>python</span></a> <a href="https://recurse.social/tags/verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>verilog</span></a> <a href="https://recurse.social/tags/c" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>c</span></a>, and in all-too-rare moments stuff like <a href="https://recurse.social/tags/haskell" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>haskell</span></a> <a href="https://recurse.social/tags/forth" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>forth</span></a> <a href="https://recurse.social/tags/agda" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>agda</span></a> and <a href="https://recurse.social/tags/prolog" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>prolog</span></a><br> <br>I've never been much for social media, usually preferring to keep interests local: a better-detailed <a href="https://recurse.social/tags/introduction" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>introduction</span></a> to follow as I figure this out 🙂</p>
Flux<p>Is 2025 the year of <a href="https://mastodon.social/tags/FPGA" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>FPGA</span></a> on the desktop? 🤔 </p><p>Please suggest interesting FPGA projects and people to inspire us for the year ahead. 🚀</p><p>I'm working on a 2D graphics accelerator in <a href="https://mastodon.social/tags/verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>verilog</span></a> and <a href="https://mastodon.social/tags/riscv" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>riscv</span></a> assembler.</p>
PipelineC<p>Come on over to the Discord channel if you want to join the conversation about this fun work 🤓 <a href="https://discord.gg/vBUtmBZcxC" rel="nofollow noopener" translate="no" target="_blank"><span class="invisible">https://</span><span class="">discord.gg/vBUtmBZcxC</span><span class="invisible"></span></a> <a href="https://fosstodon.org/tags/FPGA" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>FPGA</span></a> <a href="https://fosstodon.org/tags/raspberrypi" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>raspberrypi</span></a> <a href="https://fosstodon.org/tags/pico" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>pico</span></a>-ice <a href="https://fosstodon.org/tags/PipelineC" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>PipelineC</span></a> <a href="https://fosstodon.org/tags/HDL" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>HDL</span></a> <a href="https://fosstodon.org/tags/Verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>Verilog</span></a> <a href="https://fosstodon.org/tags/VHDL" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>VHDL</span></a></p>
PipelineC<p>Have been super pleased with the <a href="https://fosstodon.org/tags/ice40" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>ice40</span></a> <a href="https://fosstodon.org/tags/FPGA" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>FPGA</span></a> and <a href="https://fosstodon.org/tags/raspberrypi" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>raspberrypi</span></a> board that <a href="https://pico-ice.tinyvision.ai/" rel="nofollow noopener" translate="no" target="_blank"><span class="invisible">https://</span><span class="">pico-ice.tinyvision.ai/</span><span class="invisible"></span></a> sent me to experiment with. Many thanks and I look forward to putting together a talk for intro users getting started with <a href="https://fosstodon.org/tags/PipelineC" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>PipelineC</span></a> and boards like the pico-ice 🤓 <a href="https://fosstodon.org/tags/HDL" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>HDL</span></a> <a href="https://fosstodon.org/tags/Verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>Verilog</span></a> <a href="https://fosstodon.org/tags/VHDL" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>VHDL</span></a> <a href="https://fosstodon.org/tags/hardware" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>hardware</span></a> <a href="https://fosstodon.org/tags/embedded" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>embedded</span></a></p>
Alfred M. Szmidt<p>Calling all <a href="https://mastodon.social/tags/HDL" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>HDL</span></a> hackers! I need help in putting the <a href="https://mastodon.social/tags/MIT" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>MIT</span></a> <a href="https://mastodon.social/tags/CADR" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>CADR</span></a> onto a FPGA board. <a href="https://mastodon.social/tags/VHDL" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>VHDL</span></a>, <a href="https://mastodon.social/tags/Verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>Verilog</span></a>, does not matter much. Who is up for a fun challange? <a href="https://mastodon.social/tags/LispMachine" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>LispMachine</span></a></p>
Riley S. Faelan<p>In a better world, <a href="https://toot.cat/tags/Verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>Verilog</span></a> would have <code>/clk</code> instead of <code>posedge clk</code>, <code>\clk</code> instead of <code>negedge clk</code>, and <code>_clk</code> to mean 'clock is down'.</p>
Markus Osterhoff<p>… und hier noch etwas <a href="https://troet.cafe/tags/Verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>Verilog</span></a>-Quellcode:</p>
Flux<p>I have updated my guide to <a href="https://mastodon.social/tags/Verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>Verilog</span></a> Simulation with Verilator and SDL to cover Windows as well as Linux and macOS.</p><p>If your Verilog project uses graphics, I can't recommend Verilator/SDL simulation highly enough. The turnaround time is *so* fast! <a href="https://mastodon.social/tags/FPGA" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>FPGA</span></a> ⏩ <a href="https://projectf.io/posts/verilog-sim-verilator-sdl/" rel="nofollow noopener" translate="no" target="_blank"><span class="invisible">https://</span><span class="ellipsis">projectf.io/posts/verilog-sim-</span><span class="invisible">verilator-sdl/</span></a></p>
Amini Allight<p>Is it possible to multiply a clock in a Verilog testbench? It absolutely does not need to be synthesizable, this is purely for simulation<br>I can generate clocks of different frequencies with "always begin" + delays but I want to guarantee an edge alignment or a phase shift</p><p>Boosts for visibility appreciated!<br><a href="https://mastodon.gamedev.place/tags/verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>verilog</span></a> <a href="https://mastodon.gamedev.place/tags/fpga" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>fpga</span></a> <a href="https://mastodon.gamedev.place/tags/hardware" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>hardware</span></a> <a href="https://mastodon.gamedev.place/tags/openhardware" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>openhardware</span></a></p>
Topaz 🐇 📹<p>Nandland Go Board Examples</p><p><a href="https://makertube.net/videos/watch/069baaa0-e769-42b3-a691-3ca568b79148" rel="nofollow noopener" translate="no" target="_blank"><span class="invisible">https://</span><span class="ellipsis">makertube.net/videos/watch/069</span><span class="invisible">baaa0-e769-42b3-a691-3ca568b79148</span></a></p>
Alfred M. Szmidt<p>Any <a href="https://mastodon.social/tags/HDL" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>HDL</span></a> (<a href="https://mastodon.social/tags/VHDL" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>VHDL</span></a> or <a href="https://mastodon.social/tags/Verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>Verilog</span></a> doesn't matter) hackers who want to re-create the <a href="https://mastodon.social/tags/CADR" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>CADR</span></a> <a href="https://mastodon.social/tags/LispM" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>LispM</span></a> <a href="https://mastodon.social/tags/LispMachine" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>LispMachine</span></a>?</p>
Remi<p>Well after 14 years I'm laid off from Viavi. This has been a particular nightmare for me for 14 years since I was a victim of the 2008 financial meltdown and laid off then and couldn't find work for all of 2009. It was rough. </p><p>But anyway, locally fantastic staff and great people to work with. Higher management, no comment as I am negatively biased. We made some cool stuff and I will miss seeing how my current baby will turn out.</p><p>Anyhow I don't really know how far this might go, but if someone is looking for a <a href="https://universeodon.com/tags/EE" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>EE</span></a> with 25 years experience in digital design primarily with <a href="https://universeodon.com/tags/FPGA" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>FPGA</span></a> and <a href="https://universeodon.com/tags/VHDL" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>VHDL</span></a> (and a smattering of <a href="https://universeodon.com/tags/Verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>Verilog</span></a>), including verification mainly using <a href="https://universeodon.com/tags/OSVVM" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>OSVVM</span></a> and <a href="https://universeodon.com/tags/UVVM" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>UVVM</span></a> (the latter modeled after <a href="https://universeodon.com/tags/UVM" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>UVM</span></a>) please contact me, especially if you can support remote work. I do have a professional office at home, it can be YOURS (along with me of course).</p><p>(And if so inclined, boosting this for greater visibility in networks is greatly appreciated.)</p>
Ryan Baumann<p>I've made some "first/next steps" issues in my <a href="https://digipres.club/tags/AppleII" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>AppleII</span></a> <a href="https://digipres.club/tags/OpenFPGA" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>OpenFPGA</span></a> <a href="https://digipres.club/tags/AnaloguePocket" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>AnaloguePocket</span></a> core repo if any more-experienced <a href="https://digipres.club/tags/FPGA" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>FPGA</span></a> / <a href="https://digipres.club/tags/Verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>Verilog</span></a> / <a href="https://digipres.club/tags/Apple2" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>Apple2</span></a> / <a href="https://digipres.club/tags/MiSTerFPGA" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>MiSTerFPGA</span></a> devs would like to take a look and contribute: <a href="https://github.com/ryanfb/Apple-II_openFPGA/issues" rel="nofollow noopener" target="_blank"><span class="invisible">https://</span><span class="ellipsis">github.com/ryanfb/Apple-II_ope</span><span class="invisible">nFPGA/issues</span></a></p>
Pyrzout :vm:<p>Manta: An Open On-FPGA Debug Interface <a href="https://hackaday.com/2024/05/01/manta-an-open-on-fpga-debug-interface/" rel="nofollow noopener" translate="no" target="_blank"><span class="invisible">https://</span><span class="ellipsis">hackaday.com/2024/05/01/manta-</span><span class="invisible">an-open-on-fpga-debug-interface/</span></a> <a href="https://social.skynetcloud.site/tags/debuginterface" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>debuginterface</span></a> <a href="https://social.skynetcloud.site/tags/logicanalyser" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>logicanalyser</span></a> <a href="https://social.skynetcloud.site/tags/logicanalyzer" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>logicanalyzer</span></a> <a href="https://social.skynetcloud.site/tags/ToolHacks" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>ToolHacks</span></a> <a href="https://social.skynetcloud.site/tags/amaranth" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>amaranth</span></a> <a href="https://social.skynetcloud.site/tags/ethernet" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>ethernet</span></a> <a href="https://social.skynetcloud.site/tags/verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>verilog</span></a> <a href="https://social.skynetcloud.site/tags/FPGA" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>FPGA</span></a> <a href="https://social.skynetcloud.site/tags/fpga" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>fpga</span></a> <a href="https://social.skynetcloud.site/tags/uart" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>uart</span></a></p>
Markus Osterhoff<p>So, jetzt häufen sich hier endlich die Erfolge mit dem Netzwerk für den Zynq.</p><p>– online ✅<br>– UDP-Server, um Steuerbefehle zu verarbeiten ✅<br>– UDP-Client, der ein-/ausschaltbar Daten sendet ✅</p><p>– UDP-Server-Befehle zum Steuern des FPGA 👎 … kommt dann demnächst.</p><p>– gut wäre vielleicht noch, die Datenrate einstellen zu können … weil wir gar nicht immer die vollen 16.384 kHz brauchen derzeit …</p><p><a href="https://troet.cafe/tags/FPGA" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>FPGA</span></a> <a href="https://troet.cafe/tags/Zynq" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>Zynq</span></a> <a href="https://troet.cafe/tags/Verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>Verilog</span></a> <a href="https://troet.cafe/tags/SoC" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>SoC</span></a> <a href="https://troet.cafe/tags/LWIP" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>LWIP</span></a></p>
Markus Osterhoff<p>Versuch 1:<br>mit Nmax = 128 auf 16 Bit padden durch <<8</p><p>weil … der <a href="https://troet.cafe/tags/cordic" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>cordic</span></a> zwei Stellen vor dem Komma braucht, um Werte von -1,0 bis +1,0 kodieren zu können … ?</p><p>*rödel*</p><p><a href="https://troet.cafe/tags/FPGA" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>FPGA</span></a> <a href="https://troet.cafe/tags/Verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>Verilog</span></a> <a href="https://troet.cafe/tags/BinaryArithmetics" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>BinaryArithmetics</span></a></p>
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